LCD televisions (LCDTVs) are rapidly evolving creating high definition displays with more colors and resolution. Accordingly, the signal processing capabilities of LCDTVs have become increasingly more complex in order to properly process multi-bit television signals. The driver system of an LCDTV typically includes column drivers, row drivers, a timing controller, and a reference source comprising a resistor string (R-string) digital-to-analog converter (DAC) supplying voltage levels for the multi-bit resolution.
The column drivers process ten-bit digital input codes and convert them to analog levels. Although the digital input codes are ten-bits, an additional bit is typically used to drive the backside electrodes of the LCD displays with an alternating polarity. An additional DAC, a negative DAC (NDAC), is also provided as a negative reference source. To perform the requisite data conversion, a column driver for each channel of the LCD panel typically includes shift registers 102, input registers 104, data latches 106, level shifters 108, DAC decoders 110, and output buffers 112 as illustrated in FIG. 1.
Digital display data (e.g., RGB inputs) are sampled into the input registers 104 as controlled by the clock, CLK, which is applied to the shift registers 102. The data latches 106 receive one row of serial input pixel data, which they output to the level shifters 108. Level shifters 108 increase the signal power from a low-voltage signal to a high-voltage signal. The DAC decoders 110 receive the high-voltage signal, which is usually a multi-bit digital input code, and outputs a voltage level corresponding to the digital input code through buffers 112 to the highly capacitive data lines of the LCD panel.
The DAC decoders 110 take up the most area as they require a plurality of switches to decode the 10-bit input code. FIG. 2 illustrates one example of a positive DAC (PDAC) decoder 200 and a negative DAC (NDAC) decoder respectively coupled to a PDAC and an NDAC of an LCD panel. A ten-bit digital input code requires 1024 different voltage levels (e.g., 2^10=1024) and thus each channel will require 2048 different signal lines to connect the PDAC and NDAC decoders of a single channel to the PDAC and NDAC of the LCD panel. Accordingly, the metal lines and DAC decoders occupy a large amount of space on the integrated circuit for the LCD panel driver.
One attempt at reducing the overall size of a column driver is disclosed by Chih-Wen Lu and Lung-Chien Huang in “A 10-bit LCD Column Driver with Piecewise Linear Digital-to-Analog Converters”, IEEE Journal of Solid-State Circuit, Vol. 43, No. 2, February 2008, pgs 371-78, the entirety of which is herein incorporated by reference in its entirety. The Lu et al. article discloses a seven bit resistor string DAC (R-DAC) decoder and a three bit charge sharing DAC (C-DAC) decoder. The voltages for the R-DAC decoders are received from a single resistor string. The data conversion performed by the R-DAC decoders are used by the C-DACs. However, the C-DACs are not directly coupled to a common reference point increasing the chances of a mismatch occurring between adjacent channels which in turn may reduce the resolution of the LCD display device.
Accordingly, an improved architecture for an LCD driver is desirable.